#include "mem_tools.hpp"
#include "types.hpp"

Include dependency graph for registers.hpp:

This graph shows which files directly or indirectly include this file:

Macros
#define	M3_PERIPH_BASE 0xE000E000

#define	SYS_TIMER_BASE (M3_PERIHP_BASE + 0x00000010)

#define	SYS_NVIC_BASE (M3_PERIHP_BASE + 0x00000100)

#define	SYS_CTL_BASE (0x400FE000)

#define	SYS_MPU_BASE (M3_PERIHP_BASE + 0x00000D90)

#define	DEVICE_IDENT_0 (SYS_CTL_BASE)

#define	DEVICE_IDENT_1 (SYS_CTL_BASE + 0x00000004)

#define	DEVICE_CAP_0 (SYS_CTL_BASE + 0x00000008)

#define	DEVICE_CAP_1 (SYS_CTL_BASE + 0x00000010)

#define	DEVICE_CAP_2 (SYS_CTL_BASE + 0x00000014)

#define	DEVICE_CAP_3 (SYS_CTL_BASE + 0x00000018)

#define	DEVICE_CAP_4 (SYS_CTL_BASE + 0x0000001C)

#define	BRORCLT (SYS_CTL_BASE + 0x00000030)

#define	LDOPCTL (SYS_CTL_BASE + 0x00000034)

#define	SRST_CTL_0 (SYS_CTL_BASE + 0x00000040)

#define	SRST_CTL_1 (SYS_CTL_BASE + 0x00000044)

#define	SRST_CTL_2 (SYS_CTL_BASE + 0x00000048)

#define	RAW_INTR_STAT (SYS_CTL_BASE + 0x00000050)

#define	INTR_MASK_CTRL (SYS_CTL_BASE + 0x00000054)

#define	MINTR_STAT_CLR (SYS_CTL_BASE + 0x00000058)

#define	RESET_CAUSE (SYS_CTL_BASE + 0x0000005C)

#define	RCLOCK_CONFIG (SYS_CTL_BASE + 0x00000060)

#define	RCLOCK_CONFIG2 (SYS_CTL_BASE + 0x00000070)

#define	XPLL_CONFIG (SYS_CTL_BASE + 0x00000064)

#define	RCGC0 (SYS_CTL_BASE + 0x00000100)

#define	RCGC1 (SYS_CTL_BASE + 0x00000104)

#define	RCGC2 (SYS_CTL_BASE + 0x00000108)

#define	SCGC0 (SYS_CTL_BASE + 0x00000110)

#define	SCGC1 (SYS_CTL_BASE + 0x00000114)

#define	SCGC2 (SYS_CTL_BASE + 0x00000118)

#define	DCGC0 (SYS_CTL_BASE + 0x00000120)

#define	DCGC1 (SYS_CTL_BASE + 0x00000124)

#define	DCGC2 (SYS_CTL_BASE + 0x00000128)

#define	DSCLOCK_CONFIG (SYS_CTL_BASE + 0x00000144)

Macro Definition Documentation

◆ BRORCLT

#define BRORCLT (SYS_CTL_BASE + 0x00000030)

◆ DCGC0

#define DCGC0 (SYS_CTL_BASE + 0x00000120)

◆ DCGC1

#define DCGC1 (SYS_CTL_BASE + 0x00000124)

◆ DCGC2

#define DCGC2 (SYS_CTL_BASE + 0x00000128)

◆ DEVICE_CAP_0

#define DEVICE_CAP_0 (SYS_CTL_BASE + 0x00000008)

◆ DEVICE_CAP_1

#define DEVICE_CAP_1 (SYS_CTL_BASE + 0x00000010)

◆ DEVICE_CAP_2

#define DEVICE_CAP_2 (SYS_CTL_BASE + 0x00000014)

◆ DEVICE_CAP_3

#define DEVICE_CAP_3 (SYS_CTL_BASE + 0x00000018)

◆ DEVICE_CAP_4

#define DEVICE_CAP_4 (SYS_CTL_BASE + 0x0000001C)

◆ DEVICE_IDENT_0

#define DEVICE_IDENT_0 (SYS_CTL_BASE)

◆ DEVICE_IDENT_1

#define DEVICE_IDENT_1 (SYS_CTL_BASE + 0x00000004)

◆ DSCLOCK_CONFIG

#define DSCLOCK_CONFIG (SYS_CTL_BASE + 0x00000144)

◆ INTR_MASK_CTRL

#define INTR_MASK_CTRL (SYS_CTL_BASE + 0x00000054)

◆ LDOPCTL

#define LDOPCTL (SYS_CTL_BASE + 0x00000034)

◆ M3_PERIPH_BASE

#define M3_PERIPH_BASE 0xE000E000

◆ MINTR_STAT_CLR

#define MINTR_STAT_CLR (SYS_CTL_BASE + 0x00000058)

◆ RAW_INTR_STAT

#define RAW_INTR_STAT (SYS_CTL_BASE + 0x00000050)

◆ RCGC0

#define RCGC0 (SYS_CTL_BASE + 0x00000100)

◆ RCGC1

#define RCGC1 (SYS_CTL_BASE + 0x00000104)

◆ RCGC2

#define RCGC2 (SYS_CTL_BASE + 0x00000108)

◆ RCLOCK_CONFIG

#define RCLOCK_CONFIG (SYS_CTL_BASE + 0x00000060)

◆ RCLOCK_CONFIG2

#define RCLOCK_CONFIG2 (SYS_CTL_BASE + 0x00000070)

◆ RESET_CAUSE

#define RESET_CAUSE (SYS_CTL_BASE + 0x0000005C)

◆ SCGC0

#define SCGC0 (SYS_CTL_BASE + 0x00000110)

◆ SCGC1

#define SCGC1 (SYS_CTL_BASE + 0x00000114)

◆ SCGC2

#define SCGC2 (SYS_CTL_BASE + 0x00000118)

◆ SRST_CTL_0

#define SRST_CTL_0 (SYS_CTL_BASE + 0x00000040)

◆ SRST_CTL_1

#define SRST_CTL_1 (SYS_CTL_BASE + 0x00000044)

◆ SRST_CTL_2

#define SRST_CTL_2 (SYS_CTL_BASE + 0x00000048)

◆ SYS_CTL_BASE

#define SYS_CTL_BASE (0x400FE000)

◆ SYS_MPU_BASE

#define SYS_MPU_BASE (M3_PERIHP_BASE + 0x00000D90)

◆ SYS_NVIC_BASE

#define SYS_NVIC_BASE (M3_PERIHP_BASE + 0x00000100)

◆ SYS_TIMER_BASE

#define SYS_TIMER_BASE (M3_PERIHP_BASE + 0x00000010)

◆ XPLL_CONFIG

#define XPLL_CONFIG (SYS_CTL_BASE + 0x00000064)

Macros