Elara Spacecraft
Source code & API documentation for Elara spacecraft system computers
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registers.hpp
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1#pragma once
2
3#include "mem_tools.hpp"
4#include "types.hpp"
5
6/*
7 IMPORTANT REFERENCE(S):
8 lm3s6965 datasheet pg. 185
9
10*/
11
12#define M3_PERIPH_BASE 0xE000E000
13
14#define SYS_TIMER_BASE (M3_PERIHP_BASE + 0x00000010)
15#define SYS_NVIC_BASE (M3_PERIHP_BASE + 0x00000100)
16#define SYS_CTL_BASE (0x400FE000) // (M3_PERIHP_BASE + 0x00000D00)
17#define SYS_MPU_BASE (M3_PERIHP_BASE + 0x00000D90)
18
19/* Device Identification Registers*/
20#define DEVICE_IDENT_0 (SYS_CTL_BASE)
21#define DEVICE_IDENT_1 (SYS_CTL_BASE + 0x00000004)
22
23/* Device Capability Registers */
24#define DEVICE_CAP_0 (SYS_CTL_BASE + 0x00000008)
25#define DEVICE_CAP_1 (SYS_CTL_BASE + 0x00000010)
26#define DEVICE_CAP_2 (SYS_CTL_BASE + 0x00000014)
27#define DEVICE_CAP_3 (SYS_CTL_BASE + 0x00000018)
28#define DEVICE_CAP_4 (SYS_CTL_BASE + 0x0000001C)
29
30/* Power Control Registers */
31#define BRORCLT (SYS_CTL_BASE + 0x00000030)
32#define LDOPCTL (SYS_CTL_BASE + 0x00000034)
33
34/* Software Reset Control Registers*/
35#define SRST_CTL_0 (SYS_CTL_BASE + 0x00000040)
36#define SRST_CTL_1 (SYS_CTL_BASE + 0x00000044)
37#define SRST_CTL_2 (SYS_CTL_BASE + 0x00000048)
38
39/* Interrupt Registers */
40#define RAW_INTR_STAT (SYS_CTL_BASE + 0x00000050)
41#define INTR_MASK_CTRL (SYS_CTL_BASE + 0x00000054)
42#define MINTR_STAT_CLR (SYS_CTL_BASE + 0x00000058)
43
44/* Reset Register */
45#define RESET_CAUSE (SYS_CTL_BASE + 0x0000005C)
46
47/* Clock Registers */
48#define RCLOCK_CONFIG (SYS_CTL_BASE + 0x00000060)
49#define RCLOCK_CONFIG2 (SYS_CTL_BASE + 0x00000070)
50
51#define XPLL_CONFIG (SYS_CTL_BASE + 0x00000064)
52
53#define RCGC0 (SYS_CTL_BASE + 0x00000100)
54#define RCGC1 (SYS_CTL_BASE + 0x00000104)
55#define RCGC2 (SYS_CTL_BASE + 0x00000108)
56
57#define SCGC0 (SYS_CTL_BASE + 0x00000110)
58#define SCGC1 (SYS_CTL_BASE + 0x00000114)
59#define SCGC2 (SYS_CTL_BASE + 0x00000118)
60
61#define DCGC0 (SYS_CTL_BASE + 0x00000120)
62#define DCGC1 (SYS_CTL_BASE + 0x00000124)
63#define DCGC2 (SYS_CTL_BASE + 0x00000128)
64#define DSCLOCK_CONFIG (SYS_CTL_BASE + 0x00000144)
mem_tools.hpp